ASYNC17 - San Diego, May 21-24 2017

Submission Instructions

Submission Website

Submission Intructions:
To make a submission for ASYNC 2017, go to https://www.softconf.com/g/async2017/
You will need to login or register and login. Once logged in, from the login screen, click on the Make new Submission link.

Paper Templates

Please use the templates provided by IEEE (in this link) for all papers submitted to ASYNC 2017.

Call for Papers

Regular Papers

Authors are invited to submit papers on any aspect of synchronous design topics ranging from design, synthesis, and test, to asynchronous applications in system-level integration and emerging computing technologies. Topics of interest include:

  • Mixed-timed circuits, GALS systems, networks-on-chips, multi-chip interconnects, and 3D integration;
  • Elastic and latency-tolerant synchronous design;
  • Asynchronous pipelines, architectures, CPUs, and memories;
  • Asynchronous logic in ultra-low power and power-constrained systems, energy harvesting and mixed-signal/analog design;
  • Asynchrony in emerging technologies, including bio, neural, nano, and quantum computing;
  • CAD tools for asynchronous design, synthesis, analysis, and optimization;
  • Formal methods for verification and performance/power analysis;
  • Test, security, fault tolerance, and radiation-hard design;
  • Asynchronous variability-tolerant, resilient design and design for manufacturing;
  • Asynchronous design for neural networks and machine learning applications;
  • Circuit designs, case studies, comparisons, and applications.

Submissions must report original scientific work, in 6-8 pages IEEE double-column conference format, with author information concealed. Accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings.


Industrial Papers

ASYNC 2017 will include a special industrial workshop with papers and tutorials from industry on the state-of-the-art application of asynchronous designs to both existing and emerging technologies. The topics are specifically targeted at industry and include:

  • Synchronizers and clock domain crossing techniques;
  • Techniques for combining asynchronous and clocked designs;
  • CAD tools for integrating asynchronous circuits with clocked designs;
  • Circuit designs, case studies, comparisons, and applications.

We solicit 1-page to 2-page submissions for the workshop, IEEE double-column conference format. These papers will go through a separate light-weight review process. Accepted papers will be published in the IEEE digital library IEEEXplore and symposium proceedings.


Fresh Ideas Workshop

ASYNC 2017 will accommodate a special workshop to present “fresh ideas” in asynchronous design, that are not yet ready for publication. We solicit 1-to-2-page submissions for the workshop, which will go through a separate light-weight review process. Accepted submissions will be handed out at the workshop.


Important Dates

Regular Track Abstract Registration Deadline

December 2, 2016  November 25, 2016 

 Regular Track Full Paper Submission Deadline

December 16, 2016   December 2, 2016 

 Regular Track Notification of Acceptance

February 10, 2017

Fresh Ideas  Workshop Submission Deadline

February 24, 2017

 Industrial Papers Submission Deadline

February 24, 2017

Publication-Ready Final Version

March 10, 2017